Soc Logic Design Engineer

Intel Intel · Semiconductors · Bangalore, India

Senior SoC Logic Design Engineer responsible for designing and developing cutting-edge System-on-Chip (SoC) solutions for Intel products and Custom ASIC customers. This role involves RTL coding, simulation, IP integration, and optimization for performance, power, and area, with a focus on Server, Client, Networking, and AI applications. The engineer will also ensure design quality, security, and collaborate with cross-functional teams.

What you'd actually do

  1. Develop and implement logic design, register transfer level (RTL) coding, and simulation for SoC designs for Data Center/Networking/Client & AI applications
  2. Integrate IP blocks and subsystems into a full-chip SoC or discrete component design.
  3. Define and apply architecture and microarchitecture features of logic blocks under design.
  4. Perform quality checks on logic design aspects, from RTL to timing and power convergence, ensuring alignment with design goals.
  5. Write and optimize RTL to meet power, performance, area, and timing objectives while maintaining physical implementation integrity.

Skills

Required

  • RTL design
  • RTL coding
  • RTL simulation
  • SoC integration
  • system architecture
  • low-power design
  • debugging microarchitecture
  • debugging simulation
  • front-end SoC quality guardrails
  • front-end SoC efficiency guardrails

Nice to have

  • Electrical Engineering
  • Computer Engineering
  • cross-functional teams collaboration
  • analytical skills
  • problem-solving skills
  • communication skills

What the JD emphasized

  • cutting-edge System-on-Chip (SoC) solutions
  • Server, Client, Networking and AI applications
  • logic design, register transfer level (RTL) coding, and simulation
  • IP blocks and subsystems
  • architecture and microarchitecture features
  • power, performance, area, and timing objectives
  • secure development practices
  • RTL design, coding, and simulation techniques
  • low-power design, SoC integration, and system architecture
  • debugging microarchitecture and simulation
  • front-end SoC quality and efficiency guardrails