Soc Performance Modeling & Architecture Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

Seeking a SoC Performance Modeling & Architecture Engineer to define, analyze, and optimize next-generation SoCs, focusing on performance-per-watt and shaping future silicon roadmaps. Responsibilities include leveraging and maintaining performance simulators, exploring architectural space, modeling hardware/software interactions, characterizing workloads (including ML/AI), evaluating NoC and memory hierarchy, and conducting PPA trade-off studies.

What you'd actually do

  1. Leverage, and maintain execution-driven and trace-driven SoC performance simulators (e.g., using C++, SystemC, or Python).
  2. Construct scalable models to project the performance of future SoC configurations and validate architectural concepts before RTL freeze.
  3. Model the interaction between hardware subsystems and low-level software stacks to identify system-wide bottlenecks.
  4. Profile and analyze industry-standard benchmarks and real-world use cases across CPU (e.g., SPEC CPU), GPU (e.g., 3DMark, GFXBench), and Machine Learning/AI (e.g., MLPerf, LLM inference, CNNs).
  5. Evaluate Network-on-Chip (NoC) topologies, routing algorithms, arbitration schemes, and bandwidth/latency characteristics under heavy multi-master workloads.

Skills

Required

  • BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field
  • 5+ years of industry experience in SoC/Processor architecture and performance modeling
  • Strong proficiency in C/C++ and Python
  • Deep understanding of modern computer architecture, including pipelining, out-of-order execution, cache coherence protocols, and virtual memory.
  • Direct experience with performance modeling frameworks (e.g., gem5, SystemC, or proprietary cycle-accurate/cycle-approximate simulators).

Nice to have

  • Hands-on experience with post-silicon debug tools and reading hardware performance counters (e.g., ARM PMU, Intel VTune, or internal test chips).
  • Familiarity with ML frameworks (PyTorch, TensorFlow) and compiling/mapping models to specialized hardware accelerators.
  • Experience utilizing data visualization tools to present complex performance metrics cleanly to cross-functional stakeholders.

What the JD emphasized

  • 5+ years of industry experience in SoC/Processor architecture and performance modeling
  • Strong proficiency in C/C++ and Python
  • Deep understanding of modern computer architecture, including pipelining, out-of-order execution, cache coherence protocols, and virtual memory.
  • Direct experience with performance modeling frameworks (e.g., gem5, SystemC, or proprietary cycle-accurate/cycle-approximate simulators).

Other signals

  • ML accelerators
  • MLPerf
  • LLM inference