Soc Physical Design Clocking Engineer

Intel Intel · Semiconductors · Bangalore, India

SoC Physical Design Clocking Engineer responsible for next generation Server SoC designs, focusing on product pathfinding, clock distribution, and overall SoC clock implementation and sign-off. Requires experience in clocking IPs, simulations, and methodologies, with a good understanding of physical design and timing analysis.

What you'd actually do

  1. Candidate will be part of SoC Clocking team and will work on next generation of Server SoC designs.
  2. In this role, candidate will be part of product pathfinding, clock distribution and driving overall SoC clock implementation and Sign off.
  3. Responsibilities include but are not limited to the following: - Must have Experience in SoC Clock Architecture, clock distribution and system level clocking.
  4. Experience in clocking IPs PLL, DLL etc.
  5. Hands on experience with spice, clock jitter simulations and different jitter components.

Skills

Required

  • SoC Clock Architecture
  • clock distribution
  • system level clocking
  • clocking IPs PLL, DLL etc.
  • spice, clock jitter simulations
  • clocking methodologies and guidelines
  • Physical design
  • SoC timing analysis
  • Perl, TCL Scripting Skills
  • Synopsys, cadence APR/Clock implementation tools
  • Python

Nice to have

  • A good knowledge of Physical design and SoC timing analysis would be helpful.

What the JD emphasized

  • Must have Experience in SoC Clock Architecture
  • At least 10+ years of experience in SoC clock architecture