Soc Physical Design Engineer

Intel Intel · Semiconductors · Bangalore, India

Physical Design Engineer at Intel responsible for the end-to-end physical design implementation of next-generation Client SoCs, from RTL to GDS. This includes synthesis, floor planning, placement, routing, clock tree synthesis, power analysis, verification, and signoff. The role also involves performance optimization, developing and improving physical design methodologies, and automating design flows.

What you'd actually do

  1. Perform physical design implementation from RTL to GDS, creating a design database ready for manufacturing.
  2. Execute physical synthesis, floor planning, placement, routing, and clock tree synthesis using industry-standard tools such as Synopsys and Cadence.
  3. Conduct multiple power domain analysis using standard power formats like UPF or CPF.
  4. Carry out verification and signoff processes including formal equivalence verification, static timing analysis, reliability verification, layout verification, noise analysis, and structural design checks.
  5. Analyze results and recommend design optimizations to address violations and enhance product architecture.

Skills

Required

  • Physical design implementation (RTL to GDS)
  • Physical synthesis
  • Floor planning
  • Placement
  • Routing
  • Clock tree synthesis
  • Power analysis (UPF/CPF)
  • Verification and signoff processes
  • Static timing analysis
  • Layout verification
  • Scripting (Python, Perl, TCL)
  • Synopsys tools
  • Cadence tools

Nice to have

  • Problem-solving skills
  • Attention to detail
  • Organizational capabilities
  • Collaboration skills
  • Experience in driving tool, flow, and methodology enhancements
  • Familiarity with defining physical design methodologies
  • Engaging with design automation teams, vendors, and stakeholders

What the JD emphasized

  • 10+ years of experience
  • 8+ years of experience
  • Expertise in physical design tools and methodologies
  • Proficiency in scripting languages like Python, Perl, and TCL for automation and flow improvements.
  • Experience with verification and signoff processes