Soc Physical Design Implementation Lead

AMD AMD · Semiconductors · MARKHAM, Canada · Engineering

Lead SoC Physical Design Implementation for AMD's next-generation Instinct AI and data center processors, focusing on PPA optimization, sign-off, and methodology innovation including AI-driven automation for advanced nodes, chiplets, and 3D stacking.

What you'd actually do

  1. Lead SoC-level Physical Design strategy and execution for large, complex chips, including floorplanning, placement, CTS, routing, timing sign-off, and tapeout as part of the Instinct Physical Design team.
  2. Drive power optimization, PPA closure, and sign-off for advanced nodes (3nm/2nm) on multi-chip architectures with chiplets and 3D stacking.
  3. Develop and implement advanced physical design methodologies, including AI-driven and data-driven automation, to accelerate design convergence and productivity.
  4. Collaborate with cross-functional SoC, architecture, and verification teams to ensure performance, quality, and schedule goals are met.
  5. Provide technical leadership and mentorship, influencing best practices across physical design teams while continuously improving flows and execution efficiency.

Skills

Required

  • SoC Physical Design strategy and execution
  • floorplanning
  • placement
  • CTS
  • routing
  • timing sign-off
  • tapeout
  • power optimization
  • PPA closure
  • advanced nodes (3nm/2nm)
  • multi-chip architectures
  • chiplets
  • 3D stacking
  • AI-driven automation
  • data-driven automation
  • cross-functional collaboration
  • technical leadership
  • scripting languages (Tcl, Perl, Shell)

Nice to have

  • Synopsys CAD tools
  • Cadence CAD tools
  • Siemens (Mentor Graphics) CAD tools

What the JD emphasized

  • AI-driven automation
  • data-driven automation