Soc Physical Integration Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

AMD is seeking a SoC Physical Integration Engineer to work on the physical and electrical verification and tape out of AMD SoC FPGA/ACAP devices. The role involves defining integration flows, developing verification tools, designing and integrating sub-blocks, and coordinating with various engineering groups. Experience with physical implementation tools and scripting languages is preferred.

What you'd actually do

  1. Defining and developing flows and methodologies for chip level integration
  2. Developing tools for design verification or efficiency
  3. Designing (RTL and custom), verifying, and integrating FPGA/ACAP sub-blocks
  4. Coordinating activities between different design groups to ensure smooth integration
  5. Executing chip level physical verification
  6. Executing chip level electrical verification

Skills

Required

  • Bachelor’s or Master’s degree in Electrical Engineering or equivalent
  • Proficiency in scripting languages such as Perl, Python, TCL, C-shell, Make, and/or other relevant scripting languages
  • Experience with Unix/Linux environments, including basic data management and job control
  • Excellent written and verbal communication skills, with the ability to collaborate effectively across teams

Nice to have

  • Solid understanding of FPGA architecture
  • Familiarity with physical implementation with hands‑on experience using one or more industry‑standard tools Virtuoso, ICC2, FC, Innovus, or at least one of PD tools.
  • Strong foundational knowledge of circuit design, including hands‑on simulation experience with SPICE and Verilog
  • Knowledge of and/or practical experience with Place and Route (P&R) tools
  • Strong debugging and problem‑solving skills