Soc Physical Integration Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

This role is for a SoC Physical Integration Engineer at AMD, focusing on the physical and electrical verification and tape out of AMD SoC FPGA/ACAP devices. Responsibilities include defining integration flows, developing verification tools, designing/integrating sub-blocks, and coordinating with various engineering groups. The role requires a strong understanding of FPGA architecture and physical implementation tools, with experience in circuit design and scripting languages.

What you'd actually do

  1. Defining and developing flows and methodologies for chip level integration
  2. Developing tools for design verification or efficiency
  3. Designing (RTL and custom), verifying, and integrating FPGA/ACAP sub-blocks
  4. Coordinating activities between different design groups to ensure smooth integration
  5. Executing chip level physical verification
  6. Executing chip level electrical verification

Skills

Required

  • FPGA architecture
  • physical implementation
  • Virtuoso
  • ICC2
  • FC
  • Innovus
  • PD tools
  • circuit design
  • SPICE
  • Verilog
  • Place and Route (P&R) tools
  • scripting languages
  • Perl
  • Python
  • TCL
  • C-shell
  • Make
  • Unix/Linux environments
  • data management
  • job control
  • written and verbal communication skills
  • collaboration

Nice to have

  • AMD SoC FPGA/ACAP devices