Soc Product Architect, Telecom AI Ran

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Lead SoC Product Architect for their Telecom AI RAN platform, focusing on defining the architecture and roadmap for radio and distributed unit products. The role involves analyzing workloads, driving competitive analysis, synthesizing customer requirements, and collaborating with engineering teams to ensure efficient implementation of AI-native RAN applications. The ideal candidate will have extensive experience in wireless RAN/baseband architecture or SoC product definition, with a strong understanding of 3GPP RAN standards and L1/PHY algorithms.

What you'd actually do

  1. Define the SoC product family and roadmap concerning Radio Access Networks in telecommunications. Partition responsibilities for CPU, GPU, and accelerators. Set power and cost targets. Specify scalability from coordinated RU/DU appliances to cloud-hosted O-DU.
  2. Perform detailed workload and use‑case analysis pertaining to RU and DU (FR1/FR2, MIMO layers, bandwidth, carrier aggregation, CoMP, mMIMO), and map these requirements into SoC features, memory hierarchies, accelerators, and interconnect.
  3. Drive competitive analysis versus traditional baseband ASICs and alternative vRAN / O‑RAN solutions, including performance, perf/W, silicon cost, flexibility, and upgradeability; use these insights to refine SoC and system direction.
  4. Collect and synthesize customer and ecosystem requirements from operators, NEPs, and software partners, and feed them into SoC, board, and software roadmaps with clear, prioritized product requirements.
  5. Collaborate with NVIDIA’s RAN software, AI, and cloud‑native engineering teams to ensure that the SoC architecture, reference platforms, and SDKs support efficient implementation of AI‑native RAN applications and rapid adoption of new 3GPP/O‑RAN releases.

Skills

Required

  • MS in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent experience.
  • 15+ years of experience in wireless RAN/baseband architecture or SoC product definition, with significant time focused on 4G/5G L1/L2 and/or O‑RAN / vRAN systems.
  • Proven track record defining SoC or platform architectures for high‑performance communications or signal‑processing products, including hardware/software partitioning, accelerator strategy, and memory / I/O requirements.
  • Comprehensive knowledge of 3GPP RAN standards (4G/5G, NR, NR-Advanced) and O-RAN split architectures, including the functions of radio and distributed units, fronthaul, timing, and synchronization. Understanding of how these affect compute, latency, and bandwidth needs of radio and distributed units.
  • Strong knowledge of L1/PHY algorithms (OFDM, MIMO, beamforming, channel estimation, LDPC/FEC). Understand how they run on central processors, graphics processors, and dedicated accelerators. Practical experience with one commercial-grade 4G/5G PHY or MAC implementation required.

Nice to have

  • Direct involvement in architecting GPU‑ or accelerator‑based RAN or signal‑processing systems, or in bringing a major vRAN / O‑RAN product from concept to commercial deployment.
  • Experience defining or implementing AI‑native RAN use cases (e.g., AI‑assisted scheduling, channel prediction, traffic forecasting, anomaly detection, or energy optimization) and understanding their impact on RU/DU compute and memory.
  • Hands‑on experience with O‑RAN and 3GPP standardization activities, ORAN WG contributions, or multi‑vendor interoperability programs.
  • Prior customer‑facing role conducting competitive analysis, design‑ins, or technical workshops with Tier‑1 operators, NEPs, or cloud providers.

What the JD emphasized

  • 15+ years of experience in wireless RAN/baseband architecture or SoC product definition, with significant time focused on 4G/5G L1/L2 and/or O‑RAN / vRAN systems.
  • Proven track record defining SoC or platform architectures for high‑performance communications or signal‑processing products, including hardware/software partitioning, accelerator strategy, and memory / I/O requirements.
  • Comprehensive knowledge of 3GPP RAN standards (4G/5G, NR, NR-Advanced) and O-RAN split architectures, including the functions of radio and distributed units, fronthaul, timing, and synchronization. Understanding of how these affect compute, latency, and bandwidth needs of radio and distributed units.
  • Strong knowledge of L1/PHY algorithms (OFDM, MIMO, beamforming, channel estimation, LDPC/FEC). Understand how they run on central processors, graphics processors, and dedicated accelerators. Practical experience with one commercial-grade 4G/5G PHY or MAC implementation required.
  • Direct involvement in architecting GPU‑ or accelerator‑based RAN or signal‑processing systems, or in bringing a major vRAN / O‑RAN product from concept to commercial deployment.
  • Experience defining or implementing AI‑native RAN use cases (e.g., AI‑assisted scheduling, channel prediction, traffic forecasting, anomaly detection, or energy optimization) and understanding their impact on RU/DU compute and memory.

Other signals

  • GPU-accelerated AI-RAN platform
  • AI-native RAN applications
  • AI-assisted scheduling, channel prediction, traffic forecasting, anomaly detection, or energy optimization