Soc Top Level Physical Design Engineer, Annapurna Labs

Amazon Amazon · Big Tech · Cupertino, CA · Hardware Development

This role is for a Physical Design Engineer focused on custom SoCs for AWS Machine Learning servers, including Inferentia and Trainium Systems. The engineer will be responsible for full chip floorplan, placement, integration, signoff, and tapeout, collaborating with FE teams and using industry-standard EDA tools for physical verification. The role requires expertise in physical verification, semiconductor manufacturing processes, and successful tape-outs, with a focus on advanced technology nodes.

What you'd actually do

  1. Drive full chip floorplan, placement, integration, PV signoff and tapeout
  2. Collaborate with FE team to understand RTL and drive physical aspects early in design cycle
  3. Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator)
  4. Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification
  5. Debug and resolve physical verification issues in collaboration with layout and design teams

Skills

Required

  • Scripting with Python, Perl, Bash or PowerShell
  • BS + 10yrs or MS + 7yrs in EE/CS, or related field
  • 5+ in physical verification for advanced technology nodes
  • Design Flow Knowledge: Understanding of backend physical design flows for chip-top/subsystems (FC/Innovus)
  • Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
  • Strong understanding of semiconductor manufacturing processes and design rules
  • Proven track record of successful tape-outs
  • Strong communication and collaboration abilities

Nice to have

  • Experience in mentoring, leading, or managing more junior engineers
  • Experience with integration and verification in advanced nodes [5nm or below]
  • Knowledge of custom and digital design flows
  • Expertise with DFM (Design for Manufacturing) methodologies
  • Expertise in reliability verification (ESD, EM, IR drop)
  • Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.
  • Experience in extraction of design parameters, QOR metrics, and analyzing trends

What the JD emphasized

  • physical verification
  • advanced technology nodes
  • successful tape-outs