Software Development Engineer Eda at AMD

Skills

Required

Timing Constraints (SDC) & Static Timing Analysis
ASIC and/or FPGA software tools like Vivado or Quartus
Digital Design Fundamentals and applications
TCL & Python Scripting language
BS or MS in EE or CE with 2+ years of experience in digital design and/or timing closure
RTL design using Verilog/VHDL

Nice to have

EDA
AI agents
Agentic AI skills
LLM

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career. **

SOFTWARE DEVELOPMENT ENGINEER

THE ROLE:

AMD Xilinx Hyderabad is looking for a self-motivated engineer to work on creation of designs and timing closure for FPGAs. We are looking for smart, creative people who have a passion for solving complex problems.

THE PERSON:

The ideal candidate should have a strong background in RTL design using Verilog/VHDL and should have worked on FPGA software tools like Vivado or Quartus with strong foundations in timing analysis & digital design. The candidate should have a solid understanding of timing constraints, RTL coding styles and applications. The candidate will be responsible for creating complex designs and debugging Vivado Flow issues.

**REQUIRED: **** **

Timing Constraints (SDC) & Static Timing Analysis.
Strong understanding and usage of ASIC and/or FPGA software tools like Vivado or Quartus.
Strong Digital Design Fundamentals and applications
TCL & Python Scripting language
EDA will be an added advantage.
Scripting language like Tcl or Python
Knowhow of AI agents - Agentic AI skills, LLM

ACADEMIC CREDENTIALS:

1. BS or MS in EE or CE with 2+ years of experience in digital design and/or timing closure.
1. Strong background in RTL design using Verilog/VHDL.

#LI-SG2

_Benefits offered are described: _AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

_ _

This posting is for an existing vacancy.