Software Engineer Lll, Tpu, Platforms Infrastructure Engineering

Google Google · Big Tech · Taipei, Taiwan

Software Engineer III role focused on designing and building firmware for TPUs (Tensor Processing Units) on ASICs, co-designing hardware/software interfaces, developing tools for ASIC firmware updates and debugging, building simulators for ASIC verification, and architecting debuggability and telemetry systems for TPUs. The role is part of the AI and Infrastructure team, but the core responsibilities are in hardware/software co-design and embedded systems for accelerators, not direct AI model development or serving.

What you'd actually do

  1. Design and build firmware running on embedded micro-controllers with limited memory footprints on the accelerator Application-Specific Integrated Circuits (ASIC).
  2. Co-design hardware/software interface, and work with the hardware design and development teams.
  3. Design and develop tools to update and debug ASIC firmware, and enable chip bring-up and hardware debugging.
  4. Build functional or cycle-level simulators that bit-accurately model the custom accelerator ASICs, build tools and infrastructure to help ASIC design verification, tapeout, and bring-up, and develop embedded Central Processing Unit (CPU) simulators as part of the full system simulator.
  5. Architect and design debuggability mechanisms and telemetry collection systems to monitor Tensor Processing Units (TPUs), enhancing customer satisfaction and enabling rapid response, diagnosis, and mitigation of production failures.

Skills

Required

  • software development in C/C++
  • embedded software development in C/C++

Nice to have

  • data structures and algorithms
  • hardware/software co-design at the chip-level
  • architecting scalable software
  • multi-threaded designs
  • machine learning (ML)
  • security
  • confidential computing
  • high bandwidth memory (HBM)
  • peripheral component interconnect express (PCIe)
  • advanced RISC machines (ARM)