What you'd actually do

Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.

Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.

We as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

Skills

Required

Masters or PhD in Electrical Engineer or Computer Science (or equivalent experience).
Experience with VLSI algorithms development using C++.
Understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.
Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python.

Nice to have

C++14 or newer experience, such as lambdas and concurrency.
Understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA.
Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.
Highly driven to craft software towards improving PPA with a dedication to continuous improvement.
Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design.

NVIDIA's success builds on a foundation of industry leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and specialized algorithms for VLSI design. We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.). Understanding both software and hardware aspects is the key. Creativity and self-drive to explore and perfect fast, high-capacity software is required. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, it does not get any better than this!

Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We're not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles.

What you’ll be doing:

Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
We as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:

Masters or PhD in Electrical Engineer or Computer Science (or equivalent experience).
Experience with VLSI algorithms development using C++.
Understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.
Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python.

Ways to stand out from the crowd:

C++14 or newer experience, such as lambdas and concurrency.
Understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA.
Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.
Highly driven to craft software towards improving PPA with a dedication to continuous improvement.
Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design.

NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until June 8, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.