Sr. Asic Design Engineer, Cloud-scale Machine Learning Acceleration - Annapurna Labs

Amazon Amazon · Big Tech · Austin, TX · Software Development

This role is for a Sr. ASIC Design Engineer focused on designing and optimizing hardware for AWS's machine learning servers, specifically custom SoCs like AWS Inferentia. The engineer will be responsible for integrating subsystems, implementing RTL, analyzing trade-offs for performance, power, and area, and ensuring design quality for high-performance, power-efficient chips used in ML inference.

What you'd actually do

  1. integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing
  2. As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
  3. Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
  4. Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
  5. Perform lint and clock domain crossing quality checks on the design.

Skills

Required

  • Bachelor's degree in Electrical Engineering or a related field
  • 5+ years in RTL design for SOC
  • 5+ years of VLSI engineering
  • 5+ years with code quality tools including: Spyglass, LINT, or CDC

Nice to have

  • Master's degree or Ph.D. degree in Electrical Engineering or related field
  • Experience scripting for automation (e.g., Python, Perl, Ruby)
  • Experience that includes strong analytical skills, attention to detail and effective communication abilities
  • Experience with Microarchitecture, SystemVerilog RTL
  • Familiar with scripting in Python
  • Proficient with assertions
  • Good debug skills to analyze RTL test failures

What the JD emphasized

  • 5+ years in RTL design for SOC
  • 5+ years of VLSI engineering
  • 5+ years with code quality tools including: Spyglass, LINT, or CDC