Sr. Asic Design Engineer, Cloud-scale Machine Learning Acceleration Team - Annapurna Labs

Amazon Amazon · Big Tech · Cupertino, CA · Software Development

This role is for a Sr. ASIC Design Engineer focused on designing and optimizing hardware (SoCs, accelerators) for AWS's machine learning inference servers, such as AWS Inferentia. The responsibilities include RTL design, SOC integration, performance/power/area analysis, and working with various engineering teams. While the hardware is for ML acceleration, the core craft of the role is ASIC design, not AI/ML model development.

What you'd actually do

  1. As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
  2. Integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing
  3. Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
  4. Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
  5. Perform lint and clock domain crossing quality checks on the design.

Skills

Required

  • Bachelor's degree in Electrical Engineering or a related field
  • 5+ years in RTL design for SOC
  • 5+ years in VLSI engineering
  • 5+ years with code quality tools including: Spyglass, LINT, or CDC

Nice to have

  • Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
  • Master's degree in electrical engineering, computer engineering, or equivalent
  • 5+ years of practical semiconductor design work including full-chip and subsystem integration experience
  • Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints
  • Experience with automation and scripting languages such as Python
  • Familiarity with data path design, interconnects, AXI protocol
  • Good analytical, problem solving, and communication skills
  • Familiar with scripting in Python
  • Proficient with assertions
  • Good debug skills to analyze RTL test failures

What the JD emphasized

  • 5+ years in RTL design for SOC
  • 5+ years in VLSI engineering
  • 5+ years with code quality tools including: Spyglass, LINT, or CDC