Sr Asic Design Engineer - Ethernet Switch & High-speed I/o

AMD AMD · Semiconductors · Santa Clara, CA · Engineering

This role is for a Senior ASIC Design Engineer focused on Ethernet Switch & High-Speed I/O for AMD's network chips (AINIC and DPU). The engineer will be involved in front-end RTL design, integration, and collaboration with architecture and physical design teams, as well as post-silicon support. While the company mentions AI and data centers as areas of focus, the core responsibilities of this role are in ASIC design for networking hardware, not directly in AI/ML model development or deployment.

What you'd actually do

  1. Ethernet subsystem design and integration
  2. Switch fabric, buffer, and queue design and implementation
  3. Front-end RTL design and integration of high-speed I/O subsystems
  4. Collaboration with architecture, IP, and physical design teams for first-pass silicon success
  5. Post-silicon bring-up support and yield learning

Skills

Required

  • Ethernet protocols
  • switch design
  • buffer/queue management
  • high-speed I/O (SerDes) architecture, design, and verification
  • VCS simulation tool
  • Perl/Python/Shell scripting
  • SystemVerilog/Verilog RTL design