Sr Asic Design Engineer - Noc & Axi Interconnect

AMD AMD · Semiconductors · Santa Clara, CA · Engineering

This role is for an ASIC Design Engineer focused on Network-on-Chip (NoC) and AXI interconnects for high-performance network chips (AINIC and DPU). Responsibilities include design, integration, verification, and post-silicon support, collaborating with architecture, IP, and physical design teams.

What you'd actually do

  1. Network-on-Chip (NoC) design and integration
  2. AXI, ACE, and APB interface design and verification
  3. Queuing system design and implementation
  4. Collaboration with architecture, IP, and physical design teams for first-pass silicon success
  5. Post-silicon bring-up support and yield learning

Skills

Required

  • SystemVerilog/Verilog RTL design

Nice to have

  • Network-on-Chip (NoC) architecture, protocols, and design
  • AXI, ACE, and APB interface design and verification
  • Queuing system design and buffer management
  • VCS simulation tool
  • Perl/Python/Shell scripting