Sr. Eda Tools Engineer - Esd

Intel Intel · Semiconductors · Oregon, Hillsboro, United States +3

This role focuses on developing and maintaining Electronic Static Discharge (ESD) and Electrical Overstress (EOS) rule decks for Intel's advanced process technologies. The engineer will collaborate with design, reliability, and CAD teams, define QA requirements, and lead innovation in verification automation. The position requires a Master's or PhD in Electrical Engineering or Computer Engineering with experience in physical design verification, ESD PERC rule decks, and scripting.

What you'd actually do

  1. Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM) and reliability requirements.
  2. Create and maintain reliability ESD and LU design rule methodologies and specifications.
  3. Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors to define and implement new tool features and requirements.
  4. Build and execute test cases for rule debugging, validation, and signoff.
  5. Define QA requirements and drive related automation to improve robustness and efficiency of rule checks.

Skills

Required

  • Master's degree or PhD in Electrical Engineering or Computer Engineering
  • 3+ years of relevant industry experience in physical design verification
  • 2+ years' experience with ESD PERC rule decks/runset development and debugging
  • 2+ years' experience in scripting (e.g., Python, Tcl, Perl, or similar)

Nice to have

  • Creative, independent, and "out of the box" thinker with strong analytical and problem-solving abilities
  • Strong knowledge of ESD/LU PreSi models (HBM, CDM), I/O design, and related methodologies
  • Strong attention to detail and excellent organization skills
  • Ability to connect the dots across domains and propose cross disciplinary optimal solutions
  • Self-drive with strong leadership skills
  • Excellent written and verbal communication skills
  • Proven success working with cross functional and cross site teams
  • Demonstrated ability to work in a fast paced, team-oriented environment
  • Proven ability to work effectively in a dynamic, team-oriented environment
  • Experience driving cross functional and industrywide initiatives or task forces

What the JD emphasized

  • 3+ years of relevant industry experience in physical design verification (reliability, device physics, process technology, and design rules, extraction or related domains)
  • 2+ years' experience with ESD PERC rule decks/runset development and debugging (or equivalent reliability/DRC tools)
  • 2+ years' experience in scripting (e.g., Python, Tcl, Perl, or similar) for QA and flow automation