Sr. Hardware Engineer - ML Acceleration, Annapurna Labs

Amazon Amazon · Big Tech · Cupertino, CA · Hardware Development

Hardware Design Engineer role focused on the definition, design, and validation of AWS next-generation ML Chips, Cards, and server integration. The role involves designing and optimizing hardware in data centers, with a focus on PCIe and Serdes topics for custom platforms within AWS datacenters. This position requires leadership in applying new technologies to large-scale server deployments to improve product performance, quality, and cost.

What you'd actually do

  1. As a senior member of our hardware team, you will have the outstanding and meaningful opportunity to participate in the design and execution of all PCIe and Serdes topics, with the goal of creating and customized platforms that fit within AWS datacenter’s world leading technology.
  2. As a member of the Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers.
  3. You’ll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience.
  4. You’ll have high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your products performance, quality and cost.

Skills

Required

  • ASIC implementation
  • synthesis
  • STA
  • physical design
  • deep sub-micron nodes (16nm or smaller)
  • digital design in communication systems
  • full-custom analog or RF layout
  • wireless communications systems and implementation
  • Post-Silicon Flow
  • verification in communication systems
  • UVM
  • C
  • System C
  • scripting
  • emulation
  • Electrical Engineering
  • Matlab
  • chips with multiple power islands and power gating
  • multiple access systems including OFDMA, TDMA, and CDMA
  • end-to-end network system architecture from wireless physical layer to application endpoints
  • serial protocols including SPI, I2C, I3C, and UART
  • Python
  • Embedded C programming
  • communication theory
  • OFDM
  • MIMO
  • Digital/Wireless Communication Systems
  • RF engineering
  • current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
  • methodology and scripts for physical synthesis
  • taping out chips that have gone into high volume production

Nice to have

  • creating and maintaining automation frameworks for Post-Silicon Flow
  • creating and maintaining automation frameworks for Post-Silicon Flow

What the JD emphasized

  • ML Chips
  • hardware acceleration
  • custom silicon