Sr. Lead Ip/rtl Design Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Sr. Lead IP/RTL Design Engineer focused on Data Fabric and NoC architecture within AMD. The engineer will micro-architect, design, and deliver RTL components, manage power, performance, and area targets, and collaborate with architecture, verification, and physical design teams. The role involves defining features, driving technical specifications, leading discussions on core interfacing, and supporting various design and verification stages, including post-silicon debug. While the company mentions AI and data centers, the core responsibilities are in hardware design (RTL, NoC, IP) rather than AI model development or deployment.

What you'd actually do

  1. Define Data Fabric/ NoC features and capabilities required to meet SoC requirements on power, performance, Area targets.
  2. Close architecture and micro-architecture requirements, drive technical specifications for data fabric and its IP blocks to meet those requirements, and provide technical direction to execution teams
  3. Lead discussions on ARM/x86 core interfacing to AMD data fabric IPs, to match SoC requirements.
  4. Lead design on one or more domains for the data fabric implementation.
  5. Work with architects and design leads to identify and assess complex technical issues/risks and develop as well as implement solutions to achieve product requirements

Skills

Required

  • Micro-architect
  • design
  • deliver data fabric IP RTL components
  • power, performance and area management
  • communication skills
  • problem-solving skills

Nice to have

  • NoC architecture
  • CPU/GPU coherency
  • ARM/other core architecture
  • CHI protocol experience
  • analyzing NoC Fabric , CPU, or System-level Micro-Architectural features
  • power management microarchitecture
  • low power design
  • power optimization