Sr Memory Subsystem Verification Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

This role is for a Sr. Memory Subsystem Verification Engineer at AMD, focusing on pre-silicon verification of advanced Network-on-Chip (NoC) architectures and DRAM memory controller IPs (LPDDR6, HBM4). The engineer will drive verification strategies, develop simulation and formal verification environments, and collaborate with design, architecture, and software teams to ensure high-quality silicon.

What you'd actually do

  1. Drive verification of advanced NoC architectures and next-generation DRAM memory controllers (LPDDR6, DDR5, HBM4), ensuring best-in-class quality and performance
  2. Architect, develop, and optimize simulation and formal-based verification environments at both IP and SoC levels
  3. Own the full verification lifecycle: planning, execution, tracking, closure, and delivery
  4. Create and execute robust verification plans, including sophisticated testbenches and coverage-driven test strategies
  5. Partner cross-functionally with design, architecture, and software teams to define and implement scalable verification methodologies

Skills

Required

  • SystemVerilog
  • UVM
  • simulation tools (Synopsys VCS or Cadence Xcelium)
  • modern verification methodologies
  • assertion-based verification
  • coverage-driven verification

Nice to have

  • formal verification tools (VC Formal, JasperGold, or Questa Formal)
  • gate-level simulation
  • power-aware verification
  • silicon debug (tester/board level)

What the JD emphasized

  • next-generation silicon
  • advanced Network-on-Chip (NoC) architectures
  • cutting-edge DRAM memory controller IPs (LPDDR6, HBM4)
  • full verification lifecycle
  • scalable verification methodologies