Sr Mla Dv Engineer, Cloud-scale Machine Learning Acceleration - Annapurna Labs

Amazon Amazon · Big Tech · Austin, TX · Applied Science

This role is for a Senior Machine Learning Acceleration Design Verification Engineer focused on custom silicon (SOCs) for AI workloads. The engineer will be responsible for verifying these chip designs, integrating IPs, creating testplans, writing testcases, maintaining regression infrastructure, and debugging issues. The role involves working with ML accelerator designs and requires experience with System Verilog and UVM.

What you'd actually do

  1. Verify custom chip designs at the SOC level
  2. Integrate 3rd party IPs and VIPs into the SOC testbench
  3. Create comprehensive testplans, write robust random testcases, and execute coverage plans
  4. Maintain autosmoke and regression infrastructure
  5. Dive deep into bugs and triages

Skills

Required

  • Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or related fields
  • 8+ years of design verification experience using System Verilog and UVM
  • 8+ YOE in testbench development including: stimulus, checkers, assertions and coverage

Nice to have

  • Experience verifying multiple levels of design including: custom blocks, IP blocks, sub-systems, and fullchip SOC system testing.
  • Experience using multiple verification platforms.
  • Experience with C/C++ and Object-Oriented Programming.
  • Experience with scripting languages, for e.g. Python.
  • Experience with AMBA protocols, for e.g. AHB/APB/AXI
  • Experience with interconnect protocols, for e.g. PCIe and UCIe
  • Experience with memory sub-systems, including cache coherency and synchronization techniques
  • Experience with verifying complex CPU, GPU, or ML accelerator designs

What the JD emphasized

  • custom chip designs
  • ML accelerator designs