Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging

Amazon Amazon · Big Tech · Austin, TX · Hardware Development

Seeking a Sr. Package Layout Engineer to lead the end-to-end physical design of advanced IC packages for next-generation machine learning and data center ASICs. This role involves owning the package layout from floor planning through tape out and manufacturing release, driving the physical implementation of complex multi-die and advanced packaging architectures.

What you'd actually do

  1. Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
  2. Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
  3. Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high-speed signal escape routing, and decoupling capacitor placement.
  4. Perform detailed RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates and silicon interposers.
  5. Participate in die-level RDL routing and bump planning in coordination with ASIC physical design teams, ensuring the die-package interface is co-optimized for power delivery and signal routing from the earliest design stages.

Skills

Required

  • Bachelor's degree in electrical engineering, material engineering, mechanical engineering or related fields
  • 10+ years of experience in IC package layout and physical design
  • Proven track record of leading package designs from concept through tape out for complex, multi-layer organic substrates or silicon interposers
  • Hands-on expertise with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition

What the JD emphasized

  • 10+ years of experience in IC package layout and physical design
  • Proven track record of leading package designs from concept through tape out for complex, multi-layer organic substrates or silicon interposers