Sr. Physical Design Engineer, Annapurna Labs

Amazon Amazon · Big Tech · Cupertino, CA · Hardware Development

This role is for a Sr. Physical Design Engineer focused on custom SoCs for AWS Machine Learning servers, specifically AWS Inferentia and Trainium Systems. The engineer will be responsible for the design and optimization of hardware in data centers, covering the full RTL-to-GDSII flow, including synthesis, floor planning, place and route, timing closure, and physical verification. The role involves developing physical design methodologies and evaluating third-party IP, with a focus on power-performance-area tradeoffs for ML acceleration hardware.

What you'd actually do

  1. Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure
  2. Drive IO/Core subsystem/block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
  3. Develop physical design methodologies
  4. Evaluate 3rd party IP and provide recommendations
  5. Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams

Skills

Required

  • Experience scripting with Python, Perl, Bash or PowerShell
  • BS + 8yrs or MS + 6yrs in EE/CS
  • 6+ years in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm
  • Block Design using EDA tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
  • Deep understanding on sign-off activities (timing, ir/em, physical verification)

Nice to have

  • Experience in mentoring, leading, or managing more junior engineers
  • Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
  • 4+ years in integrating IP and ability to specify and drive IP requirements in the physical domain.
  • Thorough knowledge of device physics, custom/semi-custom implementation techniques
  • Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.
  • Experience in extraction of design parameters, QOR metrics, and analyzing trends

What the JD emphasized

  • ASIC Physical Design from - RTL-to-GDSII