Sr. Physical Design Verification Engineer, Annapurna Labs

Amazon Amazon · Big Tech · Cupertino, CA · Machine Learning Science

This role is for a Sr. Physical Design Verification Engineer focused on the physical verification and integration of custom SoCs for AWS Machine Learning servers, specifically AWS Inferentia and Trainium Systems. The engineer will drive full chip floorplan, integration, and physical verification sign-off, optimize methodologies using EDA tools, perform various verification checks (DRC, LVS, PERC), debug issues, and mentor junior engineers. The role requires expertise in physical verification tools and semiconductor manufacturing processes.

What you'd actually do

  1. Drive full chip floorplan, integration and physical verification sign-off and closure
  2. Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (Calibre, IC Validator)
  3. Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification, and Fill insertion
  4. Debug and resolve physical verification issues in collaboration with layout and design teams
  5. Interface with foundries for MT form, rule deck updates and violation waivers

Skills

Required

  • Python, Perl, or another scripting language
  • BS + 10yrs or MS + 7yrs in EE/CS, or related field
  • 5+ in physical verification for advanced technology nodes
  • Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
  • Strong understanding of semiconductor manufacturing processes and design rules
  • Proven track record of successful tape-outs
  • Strong communication and collaboration abilities
  • Design Flow Knowledge: Understanding of backend physical design flows (FC/Innovus)

Nice to have

  • Experience with integration and verification in advanced nodes [5nm or below]
  • Knowledge of custom and digital design flows
  • Expertise with DFM (Design for Manufacturing) methodologies
  • Expertise in reliability verification (ESD, EM, IR drop)
  • Background in layout design or custom IC development

What the JD emphasized

  • physical verification for advanced technology nodes
  • Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
  • Proven track record of successful tape-outs