Sr. Signal Integrity / Power Integrity Engineer, Annapurna Labs, Machine Learning Hardware

Amazon Amazon · Big Tech · Austin, TX · Hardware Development

Seeking a Senior SI/PI Engineer for AWS Annapurna Labs to design and validate next-generation machine learning ASICs, focusing on high-speed channel simulations, PCB layout optimization, and ensuring signal integrity for AWS datacenter platforms. Requires expertise in simulation tools, PCIe protocols, and PCB manufacturing processes.

What you'd actually do

  1. Perform end-to-end high-speed channel simulations to ensure signal integrity across complex designs.
  2. Conduct SI/PI analysis to optimize PCB layouts, minimizing losses and signal degradation.
  3. Utilize simulation tools such as ADS, MATLAB, Cadence, HFSS, and others to evaluate performance and troubleshoot issues.
  4. Work with PCIe protocols and equalization techniques (DFE, CTLE, FFE) to optimize high-speed interfaces.
  5. Analyze clock distribution and jitter, ensuring signal timing and integrity across designs.

Skills

Required

  • Deep understanding of SI concepts and strong analytical skills in signal and power integrity.
  • Hands-on experience with simulation tools such as ADS, MATLAB, Cadence, HFSS, and others.
  • Proficiency in high-speed channel simulations, including system-level modeling and validation.
  • Experience with PCIe protocols and equalization methods (DFE, CTLE, FFE).
  • Knowledge of clock distribution and jitter analysis for high-speed designs.
  • Expertise in PCB layout and board manufacturing processes, including identifying and mitigating potential issues.
  • Hands-on experience in stack-up design, including dielectric material selection, impedance control, and layer optimization.

Nice to have

  • Experience in power integrity analysis and power delivery network (PDN) optimization.
  • Familiarity with high-speed design compliance testing and validation methodologies.
  • Knowledge of EMC/EMI mitigation techniques.

What the JD emphasized

  • Deep understanding of SI concepts and strong analytical skills in signal and power integrity.
  • Hands-on experience with simulation tools such as ADS, MATLAB, Cadence, HFSS, and others.
  • Proficiency in high-speed channel simulations, including system-level modeling and validation.
  • Experience with PCIe protocols and equalization methods (DFE, CTLE, FFE).
  • Knowledge of clock distribution and jitter analysis for high-speed designs.
  • Expertise in PCB layout and board manufacturing processes, including identifying and mitigating potential issues.
  • Hands-on experience in stack-up design, including dielectric material selection, impedance control, and layer optimization.