What you'd actually do

Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result)

Develop power redux strategy such as hierarchical CG (clock gating) at multiple levels including RTL and gate level, to ensure power target attainment

Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies

Develop, adopt and automate RTL static design rule checks in collaboration with Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team

Develop and adopt FEINT design and verification infrastructure, methodology and tools

Skills

Required

RTL synthesis
PPA analysis
Power redux strategy
ECO strategy
LEC checks
RTL static design rule checks
Verilog
C/C++
Unix/Linux environment
English communication

Nice to have

Design/Fusion Compiler
Prime Time
Power Artist
PtPx
Tcl
Ruby
Perl
Python
Makefile
RTL coding techniques for competitive PPA-measured QoR
RTL coding style for clean check on design rules (LINT, CDC, etc.)
gate level circuit design
physical level design concept and methodology
VCS/Verdi

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career. **

The role:

A Front-End Silicon Design and Integration (FEINT) Engineering role in our GFX Memory Controller IP (GMCIP) team. GFX Memory controller provides high performance functions to System on Chip (SoC) products across all AMD business units such as GPU AI accelerators, graphics and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks.

The person:

A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, Power redux, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key responsibilities:

Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result)
Develop power redux strategy such as hierarchical CG (clock gating) at multiple levels including RTL and gate level, to ensure power target attainment
Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies
Develop, adopt and automate RTL static design rule checks in collaboration with Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team
Develop and adopt FEINT design and verification infrastructure, methodology and tools

Preferred experience:

Proven understanding of RTL design, synthesis, and ECO principles
Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, PtPx, etc.
Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)
Excellent skills with Unix/Linux environment
Familiar with RTL coding techniques for competitive PPA-measured QoR
Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
Good understanding of gate level circuit design and physical level design concept and methodology
Familiar with VCS/Verdi
Excellent communication skills in English (both written and oral)
Self motivated, and committed to achievement

Academic credentials:

Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or possibly a related field
Master's Degree preferred
BSc with a minimum of 5 years relevant experience, or MSc with a minimum of 3 years
#LI-JW3

_Benefits offered are described: _AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

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This posting is for an existing vacancy.