Sr. Staff Microelectronics Semiconductor Engineer

Northrop Grumman Northrop Grumman · Aerospace · Baltimore, MD +1 · Electrical

Northrop Grumman is seeking a Sr. Staff Microelectronics Semiconductor Engineer to lead thermo-mechanical and structural analysis for advanced semiconductor packaging technologies. The role involves performing 3D Finite Element Analysis (FEA) to assess stress, vibrational, warpage, and thermo-mechanical behavior, influencing design for manufacturing (DFM) guidelines, investigating root causes of failure mechanisms, and collaborating with cross-discipline teams to ensure product performance and reliability.

What you'd actually do

  1. Perform 3D Finite Element Analysis (FEA) to assess stress, vibrational, warpage, and thermo-mechanical behavior throughout advanced semiconductor packaging platforms (e.g., flip-chip, 2.5D/3D IC, chiplet integration)
  2. Influence design for manufacturing (DFM) guidelines and contribute to long-term technology roadmaps by aligning simulation predictions with JEDEC reliability standards and accelerated life testing.
  3. Investigate and identify root causes of failure mechanisms of components and device level failures driven by design parameters or manufacturing defects
  4. Provide guidance on design of experiments to define appropriate tests for test to model correlation
  5. Partner with hardware, process, and test engineering teams to translate modeling insights into viable, production-ready package designs

Skills

Required

  • Bachelor’s Degree with 14 years of experience, master’s degree with 12 years of experience, Ph.D. with 10 years of experience in Science, Technology, Engineering, Mathematics or related technical fields
  • U.S. Citizenship
  • Ability to obtain and maintain a U.S Government Secret Clearance
  • 10 years of experience working with electronic circuit schematics and component failure modes/mechanisms
  • 10+ years of hands-on experience in electronic package modeling and simulation (thermal-mechanical interactions, warpage, and reliability)
  • Minimum of 10 years of expertise in industry-standard FEA simulation tools such as ANSYS, Abaqus, or NX CAE

Nice to have

  • Active U.S Government Secret Clearance
  • Mechanical Engineering degree or equivalent industry years of experience
  • Knowledge of failure mechanisms and accelerated life testing based on JEDEC, MIL and IPC standards
  • Familiarity with semiconductor manufacturing flows, flip-chip assembly processes (e.g., reflow, underfill, molding), and failure mechanisms
  • Experience scripting and automating simulation routines using Ansys, Python, MATLAB, or equivalent tools to scale modeling capabilities
  • Ability to read and interpret electronic circuit schematics (components and circuit card assemblies) and mechanical drawings
  • Working knowledge of compound semiconductor fabrication and testing
  • Innovative, collaborative communicator with strong interpersonal skills; able to solve complex

What the JD emphasized

  • Secret Clearance
  • 10 years of experience working with electronic circuit schematics and component failure modes/mechanisms
  • 10+ years of hands-on experience in electronic package modeling and simulation (thermal-mechanical interactions, warpage, and reliability)
  • Minimum of 10 years of expertise in industry-standard FEA simulation tools such as ANSYS, Abaqus, or NX CAE