Sr. Staff/staff Design Verification Engineer

Cerebras Cerebras · Semiconductors · Headquarters +1 · Silicon

The Sr. Staff/Staff Design Verification Engineer at Cerebras will be responsible for ensuring the high-quality design of Cerebras' AI chips, which are designed for AI training and inference. This role involves developing verification strategies, creating reusable verification environments, implementing tests, managing regressions, and debugging complex issues across simulation, emulation, and silicon bring-up. The engineer will collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation to ensure first-time silicon success. The role requires deep knowledge of SystemVerilog testbench, UVM, and scripting languages like Python, with a strong emphasis on debugging and problem-solving skills.

What you'd actually do

  1. Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon.
  2. Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.
  3. Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
  4. Implement tests, manage regressions, gather coverage, and debug test failures.
  5. Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.

Skills

Required

  • SystemVerilog testbench
  • DPI
  • UVM
  • Object-oriented design
  • Software engineering practices
  • Scalable and portable testbenches
  • Verification methodologies
  • Simulators
  • Waveform viewers
  • Build and run automation
  • Coverage collection
  • Gate level simulations
  • Python
  • Perl
  • Debugging
  • Problem-solving

Nice to have

  • Pipelined processor architecture
  • BS or MS in Computer Science or Electrical Engineering

What the JD emphasized

  • high-quality design
  • works first silicon
  • Deep knowledge of SystemVerilog testbench, DPI and UVM
  • Excellent programming skills and knowledge of software engineering practices including object-oriented design
  • Experience developing scalable and portable testbenches and components
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations
  • Proficient in scripting languages such as Python or Perl
  • Good interpersonal skills and the ability to work as a standout colleague are a must
  • Extremely self-motivated and eager to solve problems
  • 10+ years of Design Verification experience