Sta Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Silicon Design Engineer at AMD, focusing on timing signoff methodology and closure for chip subsystems. It involves using EDA tools, scripting, and analyzing timing reports to ensure quality handoff for STA checks. The role is primarily in engineering and does not directly involve building AI models.

What you'd actually do

  1. Well versed with timing signoff methodology and corner definitions
  2. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
  3. Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
  4. Ensuring block/SS level Interface timing closure along DRV closure
  5. Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure

Skills

Required

  • timing signoff methodology
  • SDC issues
  • Tcl based scripting
  • Timing closure
  • DRV closure
  • timing ECO

Nice to have

  • timing closure of block/SS
  • analyzing the timing reports
  • Synopsys Design Compiler/Primetime
  • Spyglass
  • Fishtail
  • Tweaker
  • timing closure of high frequency blocks & subsystems (> Ghz range )
  • DFT modes requirements for timing signoff
  • physical design flow
  • ECO implementation
  • OCV,AOCV,POCV analysis
  • SDC construct ( clock generation , false path , multi cycle paths..)

What the JD emphasized

  • Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
  • Strong TCL/scripting knowledge is mandatory.