Sta Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for an MTS Silicon Design Engineer at AMD, focusing on the development and signoff of complex multi-mode/multi-corner timing constraints for RTL and signoff. The engineer will ensure constraint quality, drive pre-route timing checks, and perform timing closure for chip subsystems or full chips. The role requires strong knowledge of SDC, EDA timing tools, and Tcl scripting.

What you'd actually do

  1. Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
  2. Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA
  3. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
  4. Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
  5. Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure

Skills

Required

  • Development of complex multi-mode / multi-corner timing constraints
  • Ensuring constraints quality (SDC)
  • Timing signoff methodology
  • Pre-route timing checks and QoR clean up
  • SDC knowledge
  • EDA timing tool competence
  • Tcl based scripting capability
  • Timing closure
  • Full chip level Interface timing closure
  • Generating timing ECO
  • 8+ years of experience in building the timing constraints
  • Analyzing the timing reports
  • Strong TCL/scripting knowledge

Nice to have

  • Experience with Fishtail , GCA
  • Experience with Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.
  • Experience in timing closure of high frequency blocks & subsystems (> Ghz range )
  • Strong Understanding of DFT modes requirements for timing signoff
  • Good understanding of physical design flow and ECO implementation.
  • Strong understanding of OCV,AOCV,POCV analysis.

What the JD emphasized

  • Strong TCL/scripting knowledge is mandatory.