Staff Design Verification Engineer

AMD AMD · Semiconductors · Cork, Ireland · Engineering

Staff Design Verification Engineer at AMD, focusing on verifying a leading-edge PCIe Controller Sub-System Design with next-generation power optimization technology for AI Training and Inference, Gaming Consoles, Servers, and PCs. Responsibilities include functional and power verification, test plan creation, RTL verification using coverage-driven random and directed testing, and formal verification. The role requires technical leadership and collaboration with architects and designers.

What you'd actually do

  1. Work on functional or Power verification execution from test plan to verification signoff.
  2. Collaborate with architects and designers to understand the IP features.
  3. Write/Implement/Review Test Plans.
  4. Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.
  5. Own some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of SubSystem level IP interoperability.

Skills

Required

  • SystemVerilog
  • UVM
  • Object-oriented programming
  • Scripting (Ruby, Python, Perl)
  • Low-level programming languages
  • Verification execution from test plan to signoff
  • Test plan creation and review
  • Coverage driven random testing
  • Directed testing
  • Formal verification
  • PCI Express
  • AXI
  • AHB
  • AMBA
  • OCP
  • PIPE

Nice to have

  • Low Power verification techniques
  • UPF flow
  • SATA
  • USB
  • Ethernet
  • HyperTransport
  • DDR
  • AI implementation to improve verification flows
  • Simulation profiling
  • Efficiency improvements
  • Acceleration
  • HLS tools/process
  • Perl
  • Ruby
  • Makefile
  • shell
  • Mentorship and guidance to junior and senior engineers

What the JD emphasized

  • Must be a self-starter
  • Must be expert in SystemVerilog, UVM