Staff Dft Architecture & Rtl Engineer, AI Hardware

Tesla Tesla · Auto · Palo Alto, CA · Tesla AI

This role is for a Staff DFT Architecture & RTL Engineer focused on designing and implementing test structures for AI inference chips and custom AI accelerators used in Tesla's AI hardware, including the Dojo supercomputer. The role involves defining DFT architecture, RTL insertion, and leveraging agentic AI flows for automation, contributing to the hardware that powers FSD and Optimus.

What you'd actually do

  1. Define and implement full DFT architecture for complex SoC designs — ISTC, IJTAG, scan, MBIST, BISR, and JTAG boundary scan (IEEE 1149.1 / 1149.6)
  2. Drive RTL insertion and integration of Tessent-based DFT structures — ISTC, SSN, OCC, compression logic, and memory BIST
  3. Understanding and familiarity of hybrid bond testing
  4. Perform CDC/RDC checks using SpyGlass, JasperGold, or Questa CDC — identify and resolve clock and reset domain crossing violations
  5. Execute static verification flows — LINT checks, coding standard compliance, and design rule verification to ensure RTL quality and synthesizability

Skills

Required

  • DFT architecture
  • RTL insertion
  • complex SoC designs
  • ISTC
  • IJTAG
  • scan
  • MBIST
  • BISR
  • JTAG boundary scan (IEEE 1149.1 / 1149.6)
  • Siemens Tessent suite (Shell, TestKompress, MemoryBIST)
  • SSN
  • OCC
  • compression logic
  • memory BIST architectures
  • IEEE 1500
  • IEEE 1687
  • BSDL
  • ICL
  • PDL
  • CDC/RDC analysis
  • SpyGlass
  • JasperGold
  • Questa CDC
  • LINT checks
  • coding standard compliance
  • design rule verification
  • agentic AI flows

Nice to have

  • DFT architecture ownership on server-class or AI accelerator SoCs
  • hierarchical DFT for multi-die or 3D IC designs
  • low-power DFT
  • multi-Vdd
  • state retention considerations
  • hybrid bond testing

What the JD emphasized

  • DFT architecture and RTL insertion experience on complex SoCs
  • Expert-level proficiency with Siemens Tessent suite
  • Deep expertise in ISTC, SSN, OCC, compression logic, and memory BIST architectures
  • Strong command of IEEE 1149.1/1149.6, 1500, and 1687
  • Hands-on CDC/RDC analysis
  • Ability to use agentic AI flows to scale DFT insertion and validation workflows

Other signals

  • AI inference chips
  • Dojo supercomputer
  • Full Self-Driving (FSD)
  • Optimus robot
  • custom silicon
  • AI workloads
  • low-precision arithmetic
  • quantization techniques
  • hardware acceleration for machine learning
  • DFT architecture
  • RTL insertion
  • agentic AI flows