About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. Role Summary In this position you will be a key member of the ML Compiler team working on software tools to enable inference of deep learning networks hardware on Rivian Hardware Platforms. You will work closely with the Rivian Autonomy and Hardware teams and evaluate various implementation targeting for performance. You will help bring up new hardware and add support in the compiler for these hardware features. This compiler enables HW-SW codesign and would result in developing efficient building blocks for state-of-the-art machine learning models. You will be collaborating with other cross functional teams in understanding the workloads, enabling running workloads on HW and help define the future enhancements to hardware and models. Responsibilities Lead the development of an ML Compiler for mapping Autonomy ML models to Rivian Autonomy Processor (RAP1). Design and implement hardware-aware optimizations, including quantization strategies, model compression, memory-efficient representations, and operator fusion, targeted to RAP1. Collaborate with hardware teams to co-optimize model architecture and compute pipeline under real-time constraints (latency, throughput, power). Benchmark and analyze system performance across platforms and iterate to achieve optimal deployment efficiency. Partner with autonomy teams to align model optimization efforts with hardware roadmap and real-world autonomy requirements. Qualifications Ph.D. or M.S. in Computer Engineering or a related field. Excellent C/C++ and Python programming skills. Experience with various SOC platforms used for machine learning. Strong understanding of deep learning software models. Experience in compiler pipeline development preferred. Proficiency in deep learning frameworks and their low-level IRs or export formats. Experience working in aggressive design environments is preferred. Preferred Qualifications Prior experience working with hardware-software co-design, especially for autonomous or robotics platforms. Deep knowledge of numerical precision trade-offs, quantization-aware training (QAT), and dynamic/static quantization flows. Familiarity with embedded real-time constraints and hardware profiling/debugging tools. Familiarity with rearchitecting models to best suit hardware capabilities. Pay Disclosure Pay Range: The salary range for this role is $206,000 - $258,000 annually for Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for annual performance bonus and equity awards. Benefits: We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com. You can apply for this role through careers.rivian.com (or through internal-careers-rivian.icims.com if you are a current employee). This job is not expected to be closed any sooner than 6/20/2026. Equal Opportunity Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law. Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at candidateaccommodations@rivian.com. Candidate Data Privacy Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes (“Candidate Personal Data”). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. 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Staff Machine Learning Compiler Engineer
Staff Machine Learning Compiler Engineer to develop an ML Compiler for mapping Autonomy ML models to Rivian Autonomy Processor (RAP1), focusing on hardware-aware optimizations for inference performance.
What you'd actually do
- Lead the development of an ML Compiler for mapping Autonomy ML models to Rivian Autonomy Processor (RAP1).
- Design and implement hardware-aware optimizations, including quantization strategies, model compression, memory-efficient representations, and operator fusion, targeted to RAP1.
- Collaborate with hardware teams to co-optimize model architecture and compute pipeline under real-time constraints (latency, throughput, power).
- Benchmark and analyze system performance across platforms and iterate to achieve optimal deployment efficiency.
- Partner with autonomy teams to align model optimization efforts with hardware roadmap and real-world autonomy requirements.
Skills
Required
- Ph.D. or M.S. in Computer Engineering or a related field.
- Excellent C/C++ and Python programming skills.
- Experience with various SOC platforms used for machine learning.
- Strong understanding of deep learning software models.
- Proficiency in deep learning frameworks and their low-level IRs or export formats.
Nice to have
- Experience in compiler pipeline development preferred.
- Experience working in aggressive design environments is preferred.
- Prior experience working with hardware-software co-design, especially for autonomous or robotics platforms.
- Deep knowledge of numerical precision trade-offs, quantization-aware training (QAT), and dynamic/static quantization flows.
- Familiarity with embedded real-time constraints and hardware profiling/debugging tools.
- Familiarity with rearchitecting models to best suit hardware capabilities.
What the JD emphasized
- hardware-aware optimizations
- quantization strategies
- model compression
- memory-efficient representations
- operator fusion
- real-time constraints
- latency
- throughput
- power
- system performance
- deployment efficiency
- hardware roadmap
- real-world autonomy requirements
- compiler pipeline development
- hardware-software co-design
- autonomous or robotics platforms
- numerical precision trade-offs
- quantization-aware training (QAT)
- dynamic/static quantization flows
- embedded real-time constraints
- hardware profiling/debugging tools
- rearchitecting models
Other signals
- ML Compiler
- inference
- hardware-software co-design
- performance optimization