Staff Swe, Compiler Architect, System Performance Modeling

Google Google · Big Tech · Sunnyvale, CA +3

Staff SWE role focused on architecting and evolving a co-design simulation platform for next-generation ML accelerators. The role involves establishing correlation infrastructure between simulated performance and physical hardware, identifying system-level bottlenecks at the pre-silicon stage, and providing performance estimates for future ML systems. Experience with ML system architectures, compilers, and optimizing large-scale ML models is preferred.

What you'd actually do

  1. Establish and maintain high-confidence correlation infrastructure between simulated performance and physical hardware measurements (silicon).
  2. Architect and evolve the simulation layer to support deep exploration of complex, business-critical workloads (e.g., large language models, advanced kernels) and future system topologies.
  3. Identify and solve system-level hardware/software bottlenecks and optimization opportunities at the critical pre-silicon stage.
  4. Provide high-confidence lower-bound performance estimates for future ML systems and architectures.

Skills

Required

  • C++
  • Python
  • testing
  • launching software products
  • performance
  • large-scale systems data analysis
  • visualization tools
  • debugging
  • software design
  • software architecture

Nice to have

  • hardware/software co-design
  • performance analysis
  • bottleneck identification
  • pre-silicon stage
  • ML system architectures
  • compilers
  • Intermediate Representations (IRs)
  • hardware accelerators
  • enabling and optimizing large-scale ML models
  • LLMs
  • large embedding models
  • technical strategy for complex systems
  • simulation toolchains
  • hardware roadmaps
  • custom IR dialects
  • open-source compiler frameworks
  • MLIR
  • XLA
  • system level analysis
  • software-hardware mapping opportunities
  • architecting high-confidence, high-velocity system performance modeling
  • correlation infrastructure

What the JD emphasized

  • next-generation performance modeling and simulation technologies
  • critical co-design simulation platform
  • system-level performance challenges
  • ML systems
  • HW-SW co-design
  • large language models
  • performance analysis and bottleneck identification at the pre-silicon stage
  • large-scale ML models

Other signals

  • performance modeling
  • simulation technologies
  • ML accelerators
  • co-design simulation platform
  • system-level performance challenges
  • ML systems
  • HW-SW co-design
  • large language models