Static Timing Analysis (sta) Engineer – (lead or Senior)

Boeing Boeing · Aerospace · El Segundo, CA

Boeing is seeking a Static Timing Analysis (STA) Engineer for their Electronic Products team, focusing on ASICs and FPGAs for defense and security programs. The role involves pre-layout and post-layout timing analysis, constraint generation, and timing convergence throughout the ASIC cycle, collaborating with physical design teams and EDA vendors. Experience with timing tools like Synopsys Primetime and synthesis tools like Synopsys Design Compiler is required. The position requires the ability to obtain a US Security Clearance.

What you'd actually do

  1. Responsible for STA analysis and convergence throughout the ASIC cycle
  2. Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)
  3. Facilitate STA methodology in collaboration with other STA leaders
  4. Generate timing constraints for multiple ASICs and FPGAs
  5. Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis

Skills

Required

  • Timing closure on ASICs and FPGAs
  • RTL to GDS flow
  • Synopsys Primetime
  • Cadence Tempus
  • Synopsys Design Compiler
  • Cadence Genus
  • Python
  • TCL
  • Perl
  • Unix shell

Nice to have

  • Synopsys Fusion Compiler
  • Cadence LEC
  • TCM
  • Fishtail
  • Synopsys physical design AI tool experience
  • Space-based design techniques
  • Radiation mitigation
  • Design for testability (DFT)
  • Multiple scripting languages
  • Handling timing closure on multiple designs simultaneously

What the JD emphasized

  • Requires the ability to obtain a U.S. Security Clearance
  • Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
  • 5 years of experience with timing closure on ASICs and FPGAs
  • Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow
  • Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis