Systems Design Engineer

AMD AMD · Semiconductors · Shanghai, China · Engineering

AMD is seeking a Lead / Principal Systems Design Engineer with expertise in system power design for next-generation motherboard platforms. The role involves end-to-end power architecture, DC-DC power solutions, simulation, optimization, and collaboration with cross-functional teams to deliver high-quality, industry-leading technologies. The focus is on improving battery life and power efficiency across various platform components and firmware layers, with a mention of advancing AI and beyond.

What you'd actually do

  1. Own the endtoend power architecture for x86 platforms (desktop, notebook, or server), spanning APU/CPU, memory, chipset, PCIe, and auxiliary power rails.
  2. Design, simulate, and optimize high-efficiency DC-DC power solutions for battery life and high-performance CPU/APU platforms.
  3. Schematic design, PCB layout reviews, and component selection to meet power delivery requirement (e.g., voltage ripple, transient response, efficiency etc.).
  4. Collaborate with cross-functional teams (Arch, EE, thermal, layout, SI/PI etc.) to delivery motherboard reference board on time.
  5. Conduct PDN(power delivery network) simulation and analysis, ensure power integrity

Skills

Required

  • System Power Design Expert
  • solve complex technical problems
  • meticulous validation and debugging
  • system-level optimization perspective
  • Clear communication in English
  • proactive coordination across cross-functional teams
  • BS or above in Electrical/Electronic/Power Engineering, or related field
  • 10+ years of hands-on experience in power hardware design, preferably for laptop platforms.

Nice to have

  • Proficiency in mobile products, including battery technology/management, battery fuel gauge operation/calibration
  • Proficiency in charger, firmware-level settings for BIOS/UEFI and Embedded Controllers (EC).
  • Expertise in hardware power management, in-depth knowledge of System & SoC power states (ACPI, C-States, P-States) and low-power modes for peripherals (display, Wi-Fi, SSD, USB).
  • Proficiency in DC-DC converter topologies (buck, boost, multiphase), PWM controllers, MOSFET, and power stage.
  • Experience with simulation tools (e.g., Simplis, SPICE, PowerDC, Ansys SIWave).
  • Strong knowledge of PCB layout considerations for power circuits (e.g., parasitic reduction).
  • PDN and PI analysis capability is a plus
  • Familiarity with lab equipment: oscilloscopes, spectrum analyzers, and power integrity test setups.
  • Knowledge of EMI/EMC mitigation techniques in power designs.
  • Good English communication
  • Problem-solving mindset, teamwork.

What the JD emphasized

  • endtoend power architecture
  • battery life
  • power delivery requirement
  • power integrity
  • system-level power optimization
  • battery life KPI improvements
  • lightload efficiency
  • display idle power optimization
  • idle consumption
  • lowpower feature implementation
  • battery technology related research
  • battery life validation
  • idle residency
  • SoC power requirements