Technical Lead Manager, Machine Learning, Memory Subsystem Design

Google Google · Big Tech · Sunnyvale, CA +1

Lead and manage a team of engineers developing high-performance memory subsystems (including HBM) for machine learning products, focusing on custom silicon solutions for Google's hardware. This involves collaboration with cross-functional teams, IP providers, and DRAM manufacturers, and driving improvements in design methodologies.

What you'd actually do

  1. Lead, mentor and manage a team of RTL Design and DV Engineers developing DRAM subsystems including HBM.
  2. Collaborate closely with the cross-functional teams (e.g. Design for Test, Signal/Power Integrity, Packaging, Physical Design,Software, Silicon Validation, Silicon Engineering) to plan and execute throughout the development cycle.
  3. Interface with third party IP providers of memory related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects.
  4. Interface with DRAM manufacturers during the design and validation of DRAM subsystems.
  5. Drive improvements in design methodologies, processes, and quality control measures.

Skills

Required

  • semiconductor design
  • design verification
  • people management
  • DRAM-based memory subsystems design
  • RTL Design
  • DV Engineers

Nice to have

  • HBM-based memory subsystems
  • computer architecture
  • Electrical Engineering
  • Computer Engineering
  • Computer Science

What the JD emphasized

  • 15 years of experience in semiconductor design or design verification
  • 6 years of experience in people management, developing employees
  • Experience in designing or verifying DRAM-based memory subsystems