Tfm and Ppa Physical Design Engineer

Intel Intel · Semiconductors · Bangalore, India

This role is for a TFM and PPA Physical Design Engineer in the CPU team at Intel, focusing on developing and automating backend physical design flows for high-performance CPUs. Responsibilities include synthesis, place-and-route, floor planning, timing analysis, power consumption estimation, and working with EDA vendors to enhance tool capabilities. Requires a Master's degree with 6+ years of experience or a Bachelor's degree with 8+ years of experience, with expertise in physical design tools and scripting.

What you'd actually do

  1. Developing, debugging, and supporting tools, flows and methodologies covering backend physical design methodologies and flow automation for high performance blocks and full chip level using RTL2GDS standard cell level design techniques.
  2. Performing analysis of either synthesis, place-and-route, floor planning or signoff for static timing analysis on timing paths, formal equivalence verification, estimating power consumption, electrical rule checking, and circuit reliability to identify key issues.
  3. Working closely with design teams to understand and debug tool issues and constraints.
  4. Working with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.

Skills

Required

  • Masters Degree in Electrical or Computer Engineering or Bachelor's Degree
  • 6 or more years of experience in related field
  • 8 years of experience
  • Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS)

Nice to have

  • Verilog/ VHDL
  • Tcl, Perl, Python scripting

What the JD emphasized

  • at least 6 or more years of experience
  • at least 8 years of experience