Tpu Rtl Design Engineer, Networking, Inter-chip Interconnects

Google Google · Big Tech · Sunnyvale, CA +1

This role focuses on the RTL design of custom silicon (TPUs) for AI/ML hardware acceleration, specifically the inter-chip interconnects. The engineer will design, implement, and verify complex digital designs for next-generation data center accelerators, contributing to the core components that power Google's AI and machine learning workloads.

What you'd actually do

  1. Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
  2. Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
  3. Define and document the microarchitecture for complex digital designs within the TPU.
  4. Write high-quality, performant, and power-efficient RTL code, primarily in SystemVerilog.

Skills

Required

  • RTL design
  • SystemVerilog
  • ASIC design
  • Digital systems design
  • Networking IP design
  • High-speed interconnects

Nice to have

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
  • Computer architecture
  • IEEE networking standards
  • Scripting languages (Tcl, Python, Perl)
  • Digital design fundamentals
  • CDC, RDC, RTL Linting, or LEC tools

What the JD emphasized

  • 4 years of experience in high-speed ASIC design
  • Experience architecting or designing RTL solutions for digital systems
  • Experience developing networking IP across one or more layers
  • Experience with high-speed interconnects

Other signals

  • Designing custom silicon solutions for AI/ML hardware acceleration
  • Developing ASIC/SoC hardware for AI and networking accelerators
  • Designing RTL IP with a focus on chip-to-chip high-speed interconnect subsystems