Virtual Platforms & Soc Modeling Engineer

Meta Meta · Big Tech · Sunnyvale, CA +1

Develops high-level SoC hardware models using SystemC TLM and other simulation frameworks, collaborating with architects and designers. Focuses on pre-silicon platforms for architectural exploration and software/hardware co-design. Requires strong C++ and simulation framework experience. Mentions AI tool integration for workflow optimization and responsible AI practices.

What you'd actually do

  1. Design and develop high-level models of complex SoC hardware using SystemC TLM, and other simulation frameworks
  2. Collaborate with silicon architects, digital designers, and verification engineers to design and develop high-fidelity models for first-party and third-party IPs
  3. Work with architecture teams to understand SoC and IP architecture, enabling Software/Hardware co-design using pre-silicon platforms
  4. Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering

Skills

Required

  • SystemC TLM
  • C++
  • SoC components
  • virtual platform development tools
  • Python

Nice to have

  • ARM A/M series
  • RISC-V
  • DSP
  • DMA
  • Cache Hierarchy
  • DRAM
  • Network-on-chip
  • AMBA protocols
  • CMake
  • Bazel
  • Jenkins
  • GitLab CI/CD
  • GDB
  • Synopsys Virtualizer
  • Cadence Virtual Platform
  • Imperas OVP
  • ARM Fast Models
  • C++ concurrency support library
  • power and performance metrics instrumentation
  • prompt/context engineering
  • agent orchestration

What the JD emphasized

  • 6+ years of experience