Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Triton Compiler Engineer Develops Triton front-end and back-end components for Intel GPUs, focusing on creating efficient custom GPU kernels for AI workloads. Requires strong programming skills in C, C++, Python, and experience with compiler stages, code generation, and optimization techniques. | Serve | 7 |
| Senior Compiler Engineering Manager Senior Engineering Manager to lead and scale Intel's compilation technology strategy, focusing on AI workloads, heterogeneous computing, and performance portability. The role involves defining long-term direction, guiding teams, and driving delivery of compiler innovations for CPUs, GPUs, and accelerators. | — | 5 |
| GPU Thermal Management Design Engineer Seeking a Thermal Management Design Engineer to architect, simulate, and validate thermal management and fan control features for Intel dGPU products. The role involves designing and optimizing thermal solutions and platform designs, influencing upstream teams, and collaborating with various engineering disciplines and partners to ensure product delivery to technical and schedule requirements. |
| — |
| 0 |
| Senior Staff Analog Circuit Design Engineer - SerDes Senior Staff Analog Circuit Design Engineer focused on validating SerDes technologies, ensuring reliability, functionality, and performance of mixed signal designs. Responsibilities include developing validation plans, methodologies, root cause analysis, and maintaining post-silicon validation workflows. | — | 0 |
| System Simulation Module Development Engineer Seeking a Modeling Development Engineer to join Intel's modeling engineering team, focusing on integrating and validating software for microcontroller firmware and hardware models within the semiconductor product development lifecycle. Requires strong C software engineering practices and experience with source control tools. | — | 0 |
| Analog Mixed Signal Design Engineer Seeking a Senior Mixed Signal Design Engineer to lead static timing analysis and analog circuit design for next-generation mixed-signal systems. Responsibilities include driving timing closure, executing simulations, debugging testbenches, and enhancing verification methodologies. Experience with Cadence ADE and scripting for automation is required. | — | 0 |
| Senior Staff Post-Silicon Engineer Senior Staff Post-Silicon Engineer at Intel to validate SerDes technologies, focusing on functional validation plans, methodology development, root cause analysis, and infrastructure management for mixed signal designs. Requires experience in SerDes post-silicon validation, I/O principles, and test planning. | — | 0 |
| Principal Analog Circuit Design Engineer - SerDes Principal Analog Circuit Design Engineer with expertise in high-speed SerDes applications, focusing on design, development, and verification of analog circuits in advanced process nodes. The role involves floorplanning, circuit design, parameter extraction, simulation, test plan creation, and optimization for power, performance, area, timing, and yield. Requires strong foundational knowledge of analog design principles and hands-on experience with advanced FinFET CMOS processes and simulation tools. The principal engineer is expected to influence technical direction, mentor junior engineers, and drive technical strategy. | — | 0 |
| Principal Analog Circuit Design Engineer - SerDes Principal Analog Circuit Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. Requires expertise in PLL, CDR, CTLE, DFE, ADC, or TX design, and experience with advanced FinFET CMOS technologies. Role involves technical direction, mentorship, and cross-functional collaboration. | — | 0 |
| Senior Verification Engineer Senior Verification Engineer role focused on ASIC/FPGA design verification using UVM, formal methods, and coverage-driven techniques. Responsibilities include defining verification strategy, leading execution, debugging, and mentoring junior engineers. Requires 5+ years of experience in ASIC/FPGA verification. | — | 0 |
| Design Engineer – AI SoC Development Develops logic design, RTL coding, and simulation for AI SoC development, focusing on power, performance, area, and timing goals. Integrates IP blocks, performs quality checks, and supports silicon bring-up. | — | 0 |
| Senior Pre-Silicon Verification Engineer Senior Pre-Silicon Verification Engineer specializing in mixed-signal verification for semiconductor designs. Responsibilities include developing verification strategies, creating behavioral models, executing verification plans, and debugging pre-silicon environments. | — | 0 |