Tenstorrent
Semiconductors · RISC-V AI chip (Jim Keller)
- HQ
- Toronto, CA
- Founded
- 2016
- Website
- tenstorrent.com
Semiconductors · RISC-V AI chip (Jim Keller)
Currently tracking 22 active AI roles, down 42% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$500k (avg $300k).
Tenstorrent currently has 27 active AI-related job listings, with a significant majority, 81%, focused on serving infrastructure. Engineering roles comprise all of their AI hiring. The company is primarily hiring in the United States and Canada. Frequent technical tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on AI model deployment and management. In the last 30 days, Tenstorrent has not posted any new AI roles, representing a 100% decrease compared to the previous 30-day period.
Tenstorrent currently has 25 active AI-related roles in our index. The most common open titles are: Sr. Engineer, Software - AI Compiler (2), AI/ML Physical Design Flow Engineer, C++ Machine Learning Engineer, Models Training, Design Verification Lead, AI Hardware , Infrastructure and Platform Development Engineer. Most positions are in Engineering and Research.
Tenstorrent's active AI hiring is concentrated in: serving infrastructure (80%), agents (8%), application (4%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Tenstorrent is hiring AI talent in: United States (10 roles), Canada (8 roles), Serbia (4 roles), Poland (2 roles).
Job postings at Tenstorrent most frequently reference: inference infra, model serving, fine tuning, agent orchestration, vision.
In the past 30 days, Tenstorrent has posted 1 new AI-related role.
| Title | Stage | AI score |
|---|---|---|
| ML Engineer, AI Models ML Engineer focused on bringing up, validating, and optimizing AI models (LLMs, CNNs, recommendation, vision) on Tenstorrent's hardware and simulators. This role involves porting models into Tenstorrent toolchains, running experiments for accuracy/performance/stability, and debugging cross-stack issues with hardware, compiler, and runtime teams. | Serve | 8 |
| Support Engineer - AI Server Systems Support Engineer for AI Server Systems, responsible for maintenance, troubleshooting, and preventative maintenance of AI infrastructure including GPU clusters, storage, and networking equipment. Requires hardware troubleshooting skills, Linux server experience, and communication abilities in Japanese and English. | — | 5 |
| Staff Engineer, SoC RTL Engineer Tenstorrent is seeking a Staff Digital Design Engineer to define, build, and optimize high-performance chiplet-based SoC architectures. The role involves RTL development, microarchitecture, and performance/power optimization for AI hardware. |
| — |
| 0 |
| Senior Physical Design Engineer Senior Physical Design Engineer for Tenstorrent's AIDC Yayoi project, focusing on chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a system-in-package environment. Requires extensive experience in SoC/ASIC/GPU/CPU physical design, proficiency with industry-standard tools, and scripting skills. | — | 0 |
| Power Design Engineer Tenstorrent is an AI company seeking a Power Design Engineer to focus on power analysis and optimization for CPU chiplets. The role involves defining power strategies, managing power vectors, driving analysis on RTL and netlist using tools like Joules and PrimePower, and collaborating with various design teams. While the company is in the AI space, this specific role is focused on semiconductor design (CPU power) rather than direct AI/ML model development or deployment. | — | 0 |
| Verification Engineer Tenstorrent is seeking a Verification Engineer in Tokyo to ensure the functionality and performance of their System-in-package, which integrates multiple chiplets. The role involves verifying digital IP and SoC logic, building verification infrastructure, creating testbenches, and collaborating with global teams. Experience in CPU or SoC verification and knowledge of Verilog/System Verilog are required. | — | 0 |
| Senior DFT Engineer, Architecture Tenstorrent is seeking a Senior DFT Engineer to design and integrate chiplets into a System-in-package, focusing on DFT implementation for high-speed CPU core design. Responsibilities include building chip-level DFT strategies, inserting test features, collaborating with cross-functional teams, scripting EDA tools, and supporting silicon bring-up. | — | 0 |