Tenstorrent

C++ Machine Learning Engineer focused on extending and optimizing the ML training framework for custom silicon, debugging model performance, and supporting production integration.

The role involves architecting, integrating, and deploying AI/ML-driven solutions into production physical design flows for advanced semiconductor nodes. This includes creating custom CAD tools and optimizing EDA tools using data-driven and ML-based techniques to improve PPA and runtime. The engineer will also develop and enhance RTL-to-GDS methodologies.

Software Engineer on the Metal Runtime team working on low-level software for AI accelerators, focusing on scheduling, memory movement, and efficient execution across parallel processors. The role involves building and optimizing high-performance runtime systems close to the hardware.

The role focuses on optimizing the energy efficiency of RISC-V based CPUs and AI Data Centers for Tenstorrent, a company at the forefront of AI technology. The Power Architect will be responsible for power management, SoC power architecture, power delivery networks, thermal analysis, and performance trade-offs, with a specific emphasis on analyzing AI and ML workloads for performance and efficiency. This is a hybrid role based in Santa Clara, CA, with opportunities for growth and impact in the AI hardware design space.

Software Engineer role focused on developing and scaling an MLIR-based AI compiler (TT-Forge) for Tenstorrent, involving graph transformations, lowering passes, and kernel optimizations to support both training and inference on custom chip architectures.

Software Engineer role focused on developing and optimizing distributed software systems for AI and HPC clusters, specifically for distributed inference and training infrastructure. Requires strong C/C++ systems programming, distributed computing principles, and experience with MPI-based technologies.

Software Engineer role focused on building and optimizing TT-Fabric, a low-level networking library for Tenstorrent's AI compute clusters. The role involves architecting, implementing, and maintaining the networking layer that connects thousands of AI processors for distributed training and inference, optimizing protocols and data movement for maximum hardware performance.

Lead a team of Verification Engineers to validate the functionality and performance of next-generation AI hardware, focusing on AI-specific data types, compute patterns, and on-chip network validation.