Asic Verification Engineer

Snap Snap · Consumer · Eindhoven - Netherlands

ASIC Verification Engineer for AI ASICs used in Spectacles, focusing on quality, ownership of IP blocks, and driving verification methodologies. Requires expertise in UVM, SystemVerilog, and a drive to leverage AI tools for verification.

What you'd actually do

  1. Assure the overall quality of our designs, which contribute to exciting launches of wearable devices of Spectacles at Snap
  2. Take full ownership of complex IP blocks and subsystems, pioneering verification for edge AI, high-performance camera, and next-gen display IPs.
  3. Drive the entire project lifecycle from influencing specifications to developing advanced UVM environments and achieving coverage sign-off.
  4. Act as a technical bridge, collaborating cross-functionally to refine requirements and accelerate debugging efforts through expert knowledge sharing.
  5. Shape the future of our global verification methodologies, launching bold initiatives to maintain our status as a best-in-class engineering organization.

Skills

Required

  • UVM
  • SystemVerilog
  • constraint-random verification
  • coverage-driven sign-off
  • NPUs
  • image/video processing pipelines
  • custom silicon architectures
  • UVM test environments
  • RTL (SystemVerilog, Verilog, VHDL)
  • CI/CD workflows
  • revision control (Git)

Nice to have

  • Synopsys front-end suites
  • verification of different kinds of peripherals related to image/video processing (e.g. MIPI)
  • clean, efficient code
  • Exceptional interpersonal skills
  • lead, collaborate, and thrive in an independent, fast-paced environment
  • Clear, concise, and impactful communication skills (written and verbal)

What the JD emphasized

  • AI ASIC design
  • edge AI
  • custom silicon architectures
  • AI tools to automate verification