Cpu Architect, Load-store

Tenstorrent · Semiconductors · Santa Clara, CA · Performance Model

CPU Architect role focusing on the load-store unit for high-performance out-of-order RISC-V CPUs, involving design, analysis, and optimization of memory hierarchy and data prefetchers. Collaboration with hardware and software teams is key.

What you'd actually do

  1. Drive the architecture, micro-architecture, design and optimization of the CPU load-store unit for Tenstorrent’s high-performance out-of-order RISCV CPUs
  2. Propose new implementations to optimize load-store PPA
  3. Perform simulations, modeling, and performance analysis of advanced CPU features and state-of-the-art data prefetchers
  4. Collaborate with hardware and software teams to optimize memory access patterns and system performance.
  5. Stay up to date with industry trends and emerging technologies in CPU architecture and the memory subsystem

Skills

Required

  • Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience).
  • Strong understanding of computer architecture fundamentals, including memory hierarchy, cache coherence, and data prefetching
  • Familiarity with performance modeling and simulation tools (e.g., Gem5, SimpleScalar, or similar).
  • Basic knowledge of hardware description languages (e.g., Verilog, VHDL) and system-level programming (C, C++).
  • Problem-solving skills and ability to analyze complex system interactions.
  • Excellent communication and teamwork abilities.
  • Hands-on experience with performance profiling tools and benchmarking methodologies.
  • Exposure to parallel processing architectures and multi-core systems.

What the JD emphasized

  • high-performance RISC-V CPU
  • load-store unit
  • memory subsystem
  • performance analysis
  • RISC-V CPUs