Foundry Interface Engineer

Block Block · Fintech · Singapore · Remote · 12003 Hardware - Proto Prod Dev

This role focuses on managing foundry PDK/DK and design library collaterals, analyzing production wafer test data, and collaborating with internal teams and foundry partners to fine-tune semiconductor processes for ASIC design. The engineer will assess silicon data against design goals, drive process improvements, and contribute to binning strategies to maximize yield.

What you'd actually do

  1. Engage with Foundry partners/third-party vendors to manage foundry PDK/DK and design library collaterals
  2. Guide internal IP/design teams on appropriate usage of technology attributes/offerings in accordance with product requirements (e.g., performance, power, area, and cost).
  3. Collaborate with internal third-party infrastructure, customization, test-chip, methodology, and packaging and product test engineering teams for seamless execution of product bring-up and productization.
  4. Review and assess Foundry silicon data against SPICE/design goals and compile SPICE to Silicon gap analysis. Drive foundry partners on CIPs to improve foundry process to meet technology entitlement and product goals.
  5. Work with test engineers to analyze and validate production wafer data

Skills

Required

  • Foundry PDK/DK management
  • design library collateral management
  • production wafer test data analysis
  • SPICE analysis
  • DR/DRC evaluation
  • SPICE to Si assessment
  • advanced node device physics (FinFET/GAA)
  • backside power
  • product design phases
  • product KPIs
  • DTCO
  • parametric, DLY/PLY analysis/gap closure
  • low power design techniques
  • layout effects

Nice to have

  • Master's degree or PhD in Electrical Engineering, Physics, or related field
  • Production test development experience
  • Familiarity with advanced FinFET technology nodes (3nm and 2nm)
  • Familiarity with PDK and device models
  • Previous work experience at semiconductor foundries
  • Familiarity with standard cell design and layout

What the JD emphasized

  • 5 + years of post-education experience in FAB/Fabless environments, technology definition and bring-up, device/process architecture, and NPI
  • Experience with foundry design kit, SPICE, DR/DRC evaluation, SPICE to Si assessment
  • Experience with advanced node device physics (e.g. FinFET/GAA), backside power, product design phases
  • Experience with product KPIs, DTCO, and parametric, DLY/PLY analysis/gap closure