Full-chip Physical Design Verification Engineer

Tenstorrent · Semiconductors · Austin, Fort Collins +1 · Advanced Physical Design

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. This role involves leading physical verification closure, debugging issues, and collaborating with various teams to achieve successful tapeouts.

What you'd actually do

  1. drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes
  2. lead physical verification closure (DRC, LVS, ERC, etc.)
  3. debug issues using standard industry PV tools
  4. collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts

Skills

Required

  • BS/MS in Electrical/Electronics Engineering (or related)
  • 7–14 years of hands-on CPU/IP/SoC physical verification experience
  • DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.)
  • ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM)
  • solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges
  • Scripting proficiency in Python and TCL for automation and flow optimization

Nice to have

  • mentor and technical leader

What the JD emphasized

  • full-chip signoff
  • physical verification