Risc-v AI / Hpc & Agentic Software Engineer

Tenstorrent · Semiconductors · Taiwan · Architecture

This role focuses on integrating and optimizing AI/HPC software stacks on RISC-V processors, specifically leading the bring-up of a RISC-V-native agentic AI software stack including runtime orchestration and distributed execution frameworks. The engineer will work closely with hardware architects and compiler engineers to align software capabilities with RISC-V features, operating at the hardware-software boundary.

What you'd actually do

  1. integrating and optimizing Tenstorrent’s LLK (Low-Level Kernel) infrastructure for CPU execution
  2. leading the bring-up of a RISC-V-native agentic AI software stack — including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems
  3. work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features
  4. operate at the hardware–software boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrent’s RISC-V processors

Skills

Required

  • C/C++
  • systems programming
  • performance optimization
  • RISC-V architecture
  • agentic AI frameworks
  • distributed execution systems
  • orchestration platforms
  • compiler toolchains (LLVM, GCC)
  • vectorization
  • custom ISA extensions
  • accelerator integration
  • runtime systems
  • profiling
  • low-level optimization
  • hardware–software co-design

Nice to have

  • HPC software development
  • AI software development
  • micro-architectural implications

What the JD emphasized

  • RISC-V architecture
  • agentic AI software stack
  • hardware–software boundary
  • AI / HPC software stacks
  • distributed AI systems
  • orchestration frameworks
  • agentic AI architectures
  • close to hardware
  • instruction-level programming
  • runtime systems
  • low-level optimization
  • hardware–software co-design
  • scaling next-generation AI infrastructure
  • RISC-V processors
  • RISC-V CPU
  • RISC-V CPUs
  • RISC-V architecture
  • RISC-V architectural features
  • RISC-V microarchitecture
  • RISC-V processors
  • RISC-V CPU
  • RISC-V CPUs
  • RISC-V architecture
  • RISC-V architectural features
  • RISC-V microarchitecture

Other signals

  • RISC-V CPUs optimized for AI
  • agentic AI software stack
  • hardware-software boundary