Sr. Engineer, Design Verification,system Ip

Tenstorrent Tenstorrent · Semiconductors · Bangalore, India · RISC V

Senior Design Verification Engineer responsible for end-to-end verification of IOMMU IP, ensuring functional correctness and performance. Involves test planning, coverage closure, and debugging complex issues within ASIC/SoC verification using SystemVerilog and UVM. Familiarity with bus protocols and scripting for automation is required.

What you'd actually do

  1. responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP
  2. play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure
  3. Experience owning block or subsystem-level verification from test planning to sign-off
  4. Strong understanding of constrained-random verification, coverage analysis, and regression debugging
  5. Scripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements

Skills

Required

  • ASIC or SoC verification using SystemVerilog and UVM
  • debugging complex design and verification issues
  • building verification environments from scratch
  • driving coverage closure
  • standard bus protocols
  • modern verification tools
  • protocols such as AXI, ACE, CHI, or PCIe
  • Scripting experience in Python, Perl, TCL, or Bash

Nice to have

  • familiarity with standard bus protocols and modern verification tools
  • Verification of advanced CPU and memory-management related IPs used in AI/ML systems
  • Building scalable UVM environments and improving verification methodologies
  • Collaborating across architecture, RTL, and validation teams throughout the development cycle
  • Using Automation and AI-assisted tools to improve productivity and debug efficiency

What the JD emphasized

  • end-to-end verification
  • functional correctness and performance
  • coverage closure
  • block or subsystem-level verification from test planning to sign-off
  • constrained-random verification, coverage analysis, and regression debugging