Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are seeking a designer to create board-level routing studies, design mock-ups, and SI/PI modeling collateral that support advanced semiconductor package development. This role is focused on early-stage package/board co-design rather than production PCB release. The designer will work closely with signal integrity, power integrity, mechanical, and system teams to develop representative PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling.
This role is** **hybrid, based out of Santa Clara, California, Austin, Texas, Toronto Canada or New Taipei City, Taiwan.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- An experienced PCB designer looking to expand into advanced semiconductor packaging and package-board co-design.
- Comfortable working in ambiguous problem spaces and using engineering judgment to evaluate multiple implementation tradeoffs.
- Interested in understanding how package architecture, BGA design, and board implementation influence overall system performance.
- Motivated by solving complex routing, connectivity, and electrical design challenges.
- Excited to apply automation, data analytics, and emerging AI techniques to improve engineering workflows.
What We Need
- 3+ Years experience with Cadence Allegro PCB Designer.
- Experience with high-pin-count BGAs and complex connectivity requirements.
- Ability to analyze routing congestion, layer utilization, and signal escape strategies.
- Working knowledge of Signal and Power Integrity principles.
- Strong communication skills and the ability to collaborate across multiple engineering disciplines.
What You Will Learn
- How to effectively drive co-design across silicon, packages, and systems.
- Advanced packaging concepts including chiplets, 2.5D Packaging, and On/Off-Package Memory.
- Power delivery architectures ranging from traditional lateral solutions to emerging vertical power delivery approaches, including backside power delivery, integrated voltage regulators, and package embedded passives.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.